Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
Author | Srinivasan Murali |
Publisher | Springer Science & Business Media |
Release Date | 2009-05-26 |
ISBN | 1402097573 |
Pages | 198 pages |
Rating | 4/5 (77 users) |